AN SRAM (Static Random Access Memory) is a type of a semiconductor memory that stores data using a flip flop. For example, in the SRAM, data (“1” or “0”) is stored in two cross-connected CMOS inverters configured of four transistors. Also, since two transistors are required for read/write access, a memory cell in a typical SRAM is configured of six transistors. CMOS is an abbreviation of complementary MOS (Metal Oxide Semiconductor).
For example, Patent Document 1 (Japanese Patent Application Laid-Open Publication No. H11-39879) discloses that a circuit element that selectively changes a substrate potential of an SRAM unit is provided and that a threshold voltage for a MOSFET of the SRAM unit is changed by the circuit element. And, the document discloses a technique for suppressing overall power consumption as the high-speed operation of the SRAM unit is maintained by changing the threshold voltage between a write operation and a read operation.
Patent Document 2 (Japanese Patent Application Laid-Open Publication No. 2011-90782) discloses that a performance of an SRAM is improved by configuring a static memory cell by SOI (Silicon On Insulator) transistors and changing a current of each transistor by appropriately controlling a potential of a well layer on a lower side of a buried oxide (BOX) layer of each transistor.
A third example of Patent Document 2 discloses that an nMOS connected in series between a left bit line BLT and a VSS node in a memory cell and an nMOS connected in series between a right bit line BLB and the VSS node in the memory cell are at potentials of different well nodes VBN1 and VBN2, respectively. Also, a fourth example thereof discloses a configuration derived from the configuration of the third example, in which respective well nodes for left/right pMOSs in the memory cell are also controlled separately.